1. Field of the Invention
This invention relates to a time division multiplexing communications adapter, and more particularly to such an adapter, including a number of digital signal processors, which may be used as a member of an interconnected group of such adapters.
2. Background Information
A conventional DSP (Digital Signal Processor) based communications system having a capability of handling large numbers of channels on one or more network lines includes a line card to which one or more external lines may be attached and one or more DSP cards which can be used for adding processor resource to the line card. However, since network lines can carry varying numbers of information channels, and since information networks can be expected to grow and otherwise change in a number of ways, a problem with this approach is its lack of flexibility. A user of this type of system cannot vary the number of lines which can be attached to his system to match his processing capability without increasing his number of line cards.
What is needed is a communications card which has both line adapter functions and DSP resources, with such a card being readily connectable with a second communications card to increase the DSP resources available for a network line attached to the second communications card.
What is needed is a communications card which communicates with an external processor, such as the processor of a host controller card, or a system unit processor, by means of interrupts. The communications adapter may have a number of DSPs. Due to the real-time nature of processor operation, the overhead of handling interrupts may become a serious burden. When a single host, or controller, processor is connected to many DSPs in the communications card, a major overhead problem for the host processor is due to a need for context switching and due to a need to save and restore all registers for each interrupt. Problems with this burden are particularly significant when the host processor is a RISC configuration having a large number of registers to be saved.
What is needed is a method for bundling a number of interrupts to the host processor from a single DSP, so that they can be handled together.
3. Description of the Prior Art
U.S. Pat. No. 4,991,169 describes the use of a dual digital signal processor (DSP) to provide real-time links between multiple time division channels of a digital carrier system (e.g. T-1) and a host data processor. Operating only on digital signals, internally and at its interfaces to the carrier and host systems, the DSP exchanges data and control signalling information with the carrier system and data and control information with the host processor, converting the data in passage to different digital forms. At the interface to the carrier system, signals are received and transmitted in a form adapted to diverse terminal equipment of users, remotely linked to the carrier system via the switched public network. At the host interface, signals are transmitted and received in a form suited to the data process requirements of the host system (e.g. data bytes directly representing alphanumeric characters. The DSP acts as the equivalent of multiple different types of modems in performing required conversions. The DSP may also perform processing services in order to reduce the processing burden on the host system (e.g. parity checking of data, detection of specific character functions in data or specific tones in audio signals, and selective muting of voice to host storage for voice mail applications.
U.S. Pat. No. 5,553,293 describes an interprocessor interrupt unit (IIU) for processing interrupts between a remote processor and a host processor on a multiprocessor system. The IIU off-loads tasks involved in processing interrupts from the operating kernel of the remote processor. Control blocks of interrupt information and commands are stored in Data Random Access Memory (DRAM) by the remote processor. The remote processor packs a buffer of control block memory addresses in DRAM for the IIU to access to retrieve the control blocks from DRAM. The IIU receives a control block and loads the control block into registers. The IIU then issues an interrupt request to the host processor. The host processor receives the interrupt request and indicates to the IIU that the interrupt has been processed. The IIU then notifies the remote processor that the interrupt has been processed. The IIU may be programmed to notify the remote processor of completion either by an interrupt or by setting a status flag in the DRAM.
U.S. Pat. No. 5,572,695 describes a digital signal processing system including first and second logical memory mapping units coupled to first and second digital processors, respectively, and to a data storage unit. The first and second mapping units are operative to receive (i) first and second logical addresses generated by the first and second digital processors respectively and (ii) first and second address mapping information respectively, and generate first and second physical addresses such that each of the digital processors can independently access any of a plurality of memory locations within the data storage unit.